Ulrich Brenner

Address:
Ulrich Brenner
Research Institute for Discrete Mathematics
University of Bonn
Lennéstraße 2
53113 Bonn
Germany Phone: +49 - 228 - 73 87 49
E-Mail: brenner (at) or.uni-bonn.de

Fields of Interest:

Combinatorial Optimization
VLSI placement
Logic optimization

Publications:

Theses:

U. Brenner: Plazierung im VLSI-Design. Diplomarbeit, Universität Bonn, 2000
U. Brenner: Theory and Practice of VLSI Placement. Dissertation, Universität Bonn, 2005

Conference papers:

U. Brenner, J. Vygen: Faster Optimal Single-Row Placement with Fixed Ordering. Design, Automation and Test in Europe, Proceedings, IEEE 2000, 117-121
U. Brenner, A. Rohe: An Effective Congestion Driven Placement Framework. Proceedings of the International Symposium on Physical Design 2002, 6-11
U. Brenner, A. Pauli, J. Vygen: Almost Optimum Placement Legalization by Minimum Cost Flow and Dynamic Programming. Proceedings of the International Symposium on Physical Design, 2004, 2-9
U. Brenner, M. Struzyna: Faster and Better Global Placement by a New Transportation Algorithm. Proceedings of the 42nd Design Automation Conference, ACM 2005, 591-596
U. Brenner: VLSI Legalization with Minimum Perturbation by Iterative Augmentation. Design, Automation and Test in Europe, Proceedings, IEEE 2012, 1385-1390
U. Brenner, A. Hermann, N. Hoppmann, P. Ochsendorf: BonnPlace: A Self-Stabilizing Placement Framework. Proceedings of the International Symposium on Physical Design, 2015, 9-16
U. Brenner, A. Silvanus: Delay Optimization of Combinatorial Logic by AND-OR Path Restructuring. Proceedings of the Asia and South Pacific Design Automation Conference, 2022, 403-409.

Journal papers:

U. Brenner, J. Vygen: Worst-Case Ratios of Networks in the Rectilinear Plane. Networks 38 (2001), 126-139
U. Brenner, A. Rohe: An Effective Congestion Driven Placement Framework. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 22 (2003), 387-394
U. Brenner, J. Vygen: Legalizing a placement with minimum total movement. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 23 (2004), 1597-1613
U. Brenner, M. Struzyna, J. Vygen: BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 27 (2008), 1607-1620
U. Brenner: A Faster Polynomial Algorithm for the Unbalanced Hitchcock Transportation Problem. Operations Research Letters, vol. 36, 4, 408-413, 2008.
U. Brenner: BonnPlace Legalization: Minimizing Movement by Iterative Augmentation. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 32 (2013), 1215-1227
U. Brenner: γ-Soft Packings of Rectangles. Computational Geometry: Theory and Applications 70-71C (2018) pp. 49-64
U. Brenner, A. Hermann: Faster Carry Bit Computation for Adder Circuits with Prescribed Arrival Times. ACM Transactions on Algorithms, vol. 15, no. 4, article 45, 2019.
U. Brenner, A. Silvanus, J. Silvanus: Constructing depth-optimum circuits for adders and AND-OR paths. Discrete Applied Mathematics 310 (2022) 10-31.
U. Brenner, A. Silvanus: BonnLogic: Delay optimization by And-Or Path restructuring. Integration, the VLSI Journal, vol. 89, 123-133, 2023.
J. Brecklinghaus, U. Brenner, O. Kiss: Bounds on soft rectangle packing ratios. Computational Geometry: Theory and Applications 119 (2024) 102078.

Book chapter:

U. Brenner, J. Vygen: Analytical methods in VLSI placement. In: "Handbook of Algorithms for VLSI Physical Design Automation'', (C.J. Alpert, D.P. Mehta, S.S. Sapatnekar, eds.), Taylor and Francis, Boca Raton 2009, pp. 327-346

Technical Reports

U. Brenner: An Effective Algorithm for Mixed-Size VLSI Placement. Report No. 07970, Research Institute for Discrete Mathematics, University of Bonn, 2007.
U. Brenner, D. Rotter, U. Schorr: 2-Dimensional Arrangement in Rectangles. Report No. 141088, Research Institute for Discrete Mathematics, University of Bonn, 2014.

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